hardware projects
This page contains information regarding my hardware projects, and supporting bits of data including part libraries, EDA software job aids and HOWTOs. Information contained here is free to use for educational and non-commercial purposes. No warranty given or implied. All rights reserved where applicable.
Here are some Eagle part libraries that I wish I had when I started with Eagle but had to create from scratch. Creating libraries in Eagle is a little tricky for first-timers so please feel free to use mine to jump right to the design phase of your project! Updated as my needs require, largely focusing on legacy DIP/DIL through-hole parts.
Alliance Memory (DIP parts only, rev 4/10/16)
Rockwell R6500 Microcomputer System (complete, rev 4/14/16)
Texas Instruments TMS9900 Family (common parts, rev 4/14/16)
6502 SBC
My first single-board computer project designed from scratch! Rockwell R6502 CPU clocked at 2 MHz with a crystal oscillator, 48K of accessible system memory, 8K ROM, one 6522 VIA (work-in-progress) and one 6551 ACIA to run the console TTY.
The memory map of the 6502 SBC is pretty simple. Of course, where the RAM and ROM sit in memory generally is dictated by the design of the CPU: where it expects to find reset and IRQ vectors, and where it expects to keep the stack. In the case of the 6502, RAM sits at the bottom of the address space and ROM at the top.
0x0000-0x07FF32 kW base RAM
0x0800-0xBFFF16 kW expansion RAM
0xC000-0xDFFFHole for memory mapped I/O
0xE000-0xFFFF8 kW ROM
All leads on the breadboard are cut to length from my huge jar of 26 gauge wire remnants. The best is when you can save a few lengths of 25 or 50 pair telephone cable from the trash! This helps to keep the wiring clean and the runs nice and short.
The layout on the breadboard has address decode logic up top in all three panes of the breadboard, with a few hex inverter ICs in the center serving multiple functions (reset pulse conditioning, clock generation, address decode, etc). Serial line driver, ACIA and VIA are located on the left hand pane of the breadboard. The 6502 CPU and 555 timer based reset circuit are located in the bottom half of the center pane, while RAM and ROM occupy the right hand pane of the breadboard.
I'm still working on integrating the VIA in Rev3 so the system is heavily instrumented. Otherwise, the hardware and software is generally far enough along so as to not require a logic analyzer for debugging.
[6502 SBC Rev 3 on the Bench]

A look at Rev3 on the bench

A fully featured ROM monitor includes all required basic functionality including examine, deposit, fill, dump, execute and full online help. The monitor software was written in 6502 assembly and uses around 2K of the 8K ROM. Callable facilities are provided for TTY input and output with ample space in ROM for future additions.
[6502 SBC Console TTY with Monitor]

6502 SBC Monitor V2.0 displaying help

More information coming soon as I finish re-drawing the schematic in Eagle from TinyCAD and wrap up a few bug fixes in my monitor code. The current schematic from TinyCAD is available below.
6502 SBC Rev 3 Schematic (PDF format - updated 4/15/16 - caught an error)
If trouble getting the ACIA to work reliably on a breadboard, remove caps C5 and C6 and connections to ground on ACIA XTLI and XTLO pins (plenty of stray capacitance on the breadboard!) The 3.3K pull-up on the IRQ line may also need to be removed for reliable operation (testing continues).
Once the schematic has been fully re-drawn in Eagle, I can lay out a PCB and send away to a prototype house to have a short run produced. Layout files will be made available when complete.
I use a combination of nedit and the as65 cross-assembler on Linux for development and build of the monitor software. Frank's Cross Assemblers are free and work great. Highly recommended!
V2.0 Monitor source (known bug in dump command needs to be fixed) build script
TMS 9995 SBC
Coming soon!